module fpga_top (
    input  xtal_clk,
    input  arst_n,
    input  uart_rx,
    output uart_tx,
    output sig_o,
    output rst_led_o
);

  localparam integer XTAL_CLK_FREQ = 27000000;
  localparam integer SYS_CLK_FREQ = 3000000;

  wire sys_clk;

  clk_div #(
      .DIV_FACTOR(XTAL_CLK_FREQ / SYS_CLK_FREQ)
  ) gen_sys_clk (
      .rst_n  (arst_n),
      .clk_in (xtal_clk),
      .clk_out(sys_clk)
  );

  siggen_top siggen_inst (
      .sys_clk(sys_clk),
      .arst_n(arst_n),
      .uart_rx(uart_rx),
      .uart_tx(uart_tx),
      .sig_o(sig_o)
  );

  assign rst_led_o = ~arst_n;

endmodule
